R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 77

MCU 256K FLASH 48K 144-LQFP

R4F24268NVFQV

Manufacturer Part Number
R4F24268NVFQV
Description
MCU 256K FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24268NVFQV

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
R4F24268NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2426, H8S/2426R, H8S/2424 Group
Note:
2.1.2
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
• More general registers and control registers
• Expanded address space
• Enhanced addressing
• Enhanced instructions
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Instruction
MULXU
MULXS
CLRMAC
LDMAC
STMAC
Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
Normal mode supports the same 64-Kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
A multiply-and-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
*
Differences from H8/300 CPU
The number of execution states is incremented following a MAC instruction.
In addition, there are differences in address space, CCR and EXR register functions,
power-down modes, etc., depending on the model.
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
CLRMAC
LDMAC ERs, MACH
LDMAC ERs, MACL
STMAC MACH, ERd
STMAC MACL, ERd
Execution States
H8S/2600
2*
2*
3*
3*
1*
1*
1*
1*
1*
H8S/2000
12
20
13
21
Not supported
Page 47 of 1372
Section 2 CPU

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