R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 299

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
Section 6 Bus Controller (BSC)
6.8.13
Refresh Control
This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used.
In addition, self-refreshing can be executed when the chip enters the software standby state.
Refresh control is enabled when any area is designated as continuous synchronous DRAM space
in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
(1)
Auto Refreshing
To select auto refreshing, set the RFSHE bit to 1 in REFCR.
With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0
in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.
Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval
specification for the synchronous DRAM used.
When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings
should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown
in figure 6.66.
Since the refresh counter operation is the same as the operation in the DRAM interface, see
section 6.7.12, Refresh Control.
When the continuous synchronous DRAM space is set, access to external address space other than
continuous synchronous DRAM space cannot be performed in parallel during the auto refresh
period, since the setting of the CBRM bit of REFCR is ignored.
REJ09B0466-0350 Rev. 3.50
Page 269 of 1372
Jul 09, 2010