MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 32

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ADDR[23:11] —Base Address Field
3.5.4 Option Registers
CSORBT —Chip-Select Option Register Boot ROM
CSOR[10:0] —Chip-Select Option Registers
MODE —Asynchronous/Synchronous Mode
BYTE —Upper/Lower Byte Option
32
RESET:
RESET:
MODE
MODE
15
15
0
0
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block. The value of the base address must be a
multiple of block size. Base address register diagrams show how base register bits correspond to ad-
dress lines.
The option registers contain eight fields that determine timing of and conditions for assertion of chip-
select signals. For a chip-select signal to be asserted, all bits in the base address register must match
the corresponding internal upper address lines, and all conditions specified in the option register must
be satisfied. These conditions also apply to providing DSACK or autovector support.
CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera-
tions from peripheral memory devices.
The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
The DSACK field is not used in synchronous mode because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an ECLK cycle is pending.
This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
0 = Asynchronous mode selected (chip-select assertion determined by internal or external bus con-
1 = Synchronous mode selected (chip-select assertion synchronized with ECLK signal)
14
14
0
1
trol signals)
BYTE
BYTE
13
13
0
1
Block Size Field
12
12
0
1
R/W
R/W
Freescale Semiconductor, Inc.
000
001
010
011
100
101
110
111
11
11
0
For More Information On This Product,
1
STRB
STRB
10
10
0
0
Go to: www.freescale.com
0
9
1
9
Block Size
128 K
256 K
512 K
16 K
64 K
1 M
2 K
8 K
0
1
DSACK
DSACK
0
0
Address Lines Compared
0
6
1
6
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
0
5
1
5
SPACE
SPACE
0
4
1
4
0
3
0
3
$YFFA4E–$YFFA76
IPL
IPL
0
0
MC68331TS/D
$YFFA4A
0
1
0
1
AVEC
AVEC
0
0
0
0