MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 35

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.6 General-Purpose Input/Output
PORTE0, PORTE1 —Port E Data Register
DDRE — Port E Data Direction Register
PEPAR — Port E Pin Assignment Register
MC68331TS/D
RESET:
RESET:
RESET:
15
15
15
SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs de-
scribe registers that control the ports.
A write to the port E data register is stored in the internal data latch and, if any port E pin is configured
as an output, the value stored for that bit is driven on the pin. A read of the port E data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the register.
The port E data register is a single register that can be accessed in two locations. When accessed at
$YFFA11, the register is referred to as PORTE0; when accessed at $YFFA13, the register is referred
to as PORTE1. The register can be read or written at any time. It is unaffected by reset.
The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input. This register can be read or written at any
time.
The bits in this register control the function of each port E pin. Any bit set to one configures the corre-
sponding pin as a bus control signal, with the function shown in the following table. Any bit cleared to
zero defines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
Data bus bit 8 controls the state of this register following reset. If DATA8 is set to one during reset, the
register is set to $FF, which defines all port E pins as bus control signals. If DATA8 is cleared to zero
during reset, this register is set to $00, configuring all port E pins as I/O pins.
Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the
corresponding pin to be a bus control signal.
NOT USED
NOT USED
NOT USED
PEPAR Bit
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 16 Port E Pin Assignments
Go to: www.freescale.com
Port E Signal
8
8
8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8
DDE7
PE7
7
U
7
0
7
DDE6
PE6
U
6
6
0
6
DDE5
Bus Control Signal
PE5
U
5
5
0
5
DSACK1
DSACK0
DDE4
AVEC
RMC
PE4
SIZ1
SIZ0
U
AS
DS
4
4
0
4
DDE3
PE3
U
3
3
0
3
$YFFA11, $YFFA13
DDE2
PE2
U
2
2
0
2
DDE1
PE1
U
1
$YFFA15
1
0
$YFFA17
1
DDE0
PE0
0
U
0
0
0
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