M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 181

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
Figure 13.17 Base Timer Reset operation by INT1
6
Figure 13.15 Base Timer Reset operation by Base Timer Reset Register
Figure 13.16 Base Timer Reset operation by G1PO0 register
0
1
C
9
13.1.1 Base Timer Reset Register(G1BTRR)
NOTE:
1 .
B
2 /
1. INT1 Base Timer reset does not generate a Base Timer interrupt. INT1 may generate an interrupt if enabled.
0
2
9
1
________
M
0
The G1BTRR register provides the capability to reset the base timer when the base timer count value
matches the value stored in the G1BTRR register. The G1BTRR register is enabled by the RST4 bit
in the G1BCR0 register. This function is identical in operation to the G1PO0 base timer reset that is
enabled by the RST1 bit in the G1BCR0 reigster. If the free-running operation is not selected, the
channel 0 can be used for a waveform generation when the base timer is reset by the G1BTRR
register. Do not enable bits RST1 and RST4 simultaneously.
G
1
r a
0 -
o r
3 .
1
u
Base timer overflow request
NOTE:
, 0
Base timer
1
p
2
Base timer
G1PO0
1. Following conditions are required to generate a base timer overflow request by resetting the base timer.
G1IR0
2
RST1
0
P8
0
If the IT bit is set to 0: 07FFF
If the IT bit is set to 1: 07FFF
7
RST2
Base timer interrupt
G1BTRR register
(Base timer reset register)
3
/INT1
page 155
Base timer
RST4
f o
4
5
(1)
8
16
16
m - 2
m 0FFFE
m
m - 2
0FFFE
m - 2
m - 1
16
16
_______
m - 1
or 0BFFF
m - 1
16
m
m
m
m 0FFFE
m
m
m + 1 0000
________
m + 1 0000
m + 1 0000
16
16
16
16
0001
0001
0001
16
16
16