M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 334

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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17.7 Return from Bus off Function
17.8 Time Stamp Counter and Time Stamp Function
17.9 Listen-Only Mode
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When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by
setting the RetBusOff bit in the C0CTLR register to 1 (Force return from bus off). At this time, the error state
changes from bus off state to error active state. If the RetBusOff bit is set to 1, registers C0RECR and
C0TECR are initialized and the State_Reset bit in the C0STR register is set to 0 (The CAN module is not in
error bus off state). However, registers of the CAN module such as C0CONR register and the content of
each slot are not initialized.
When the C0TSR register is read, the value of the time stamp counter at the moment is read. The period of
the time stamp counter reference clock is the same as that of 1 bit time that is configured by the C0CONR
register. The time stamp counter functions as a free run counter.
The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference
clock. Use the TSPreScale bit in the C0CTLR register to select the divide-by-n value.
The time stamp counter is equipped with a register that captures the counter value when the protocol
controller regards it as a successful reception. The captured value is stored when a time stamp value is
stored in a reception slot.
When the RXOnly bit in the C0CTLR register is set to 1, the module enters listen-only mode.
In listen-only mode, no transmission -- data frames, error frames, and ACK response -- is performed to bus.
When listen-only mode is selected, do not request the transmission.
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