M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 237

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
0
Figure 14.30 Bus Collision Detect Function-Related Bits
1
9
C
1 .
B
2 /
0
2
This diagram applies to the case where the IOPOL is set to 1 (reversed)
9
1
Transfer clock
Transfer clock
M
RxD2
TxD2
Timer A0
TxD2
TxD2
TxD2
RxD2
BCNIC register
IR bit (Note)
U2C1 register
TE bit
CLK2
RxD2
0
Transfer clock
(3) The SSS bit in the U2SMR register (Transmit start condition select)
(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select)
(2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
G
1
r a
NOTES:
0 -
o r
3 .
If SSS bit is set to 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD2
1
1: The falling edge of RxD2 when the IOPOL is set to 0; the rising edge of RxD2 when the IOPOL is set to 1.
2: The transmit condition must be met before the falling edge (Note 1) of RxD.
u
, 0
1
p
2
2
0
0
7
Transmission enable condition is met
page 211
(Note 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
f o
4
ST
ST
Input to TA0
5
8
ST
ST
D0
D0
D0
D0
IN
D1
D1
D1
D1
.
D2
D2
A0 (one-shot timer mode) underflows
If ABSCS is set to 1, bus collision is determined when timer
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
If ACSE bit is set to 1
automatically clear when bus collision
occurs), the TE bit is cleared to 0
(transmission disabled) when
the IR bit in the BCNIC register is
set to 1 (unmatching detected).
D6
D7
D7
D7
D7
D8
D8
D8
.
D8
SP
SP
SP
SP