M30290FAHP#U5A Renesas Electronics America, M30290FAHP#U5A Datasheet - Page 494

• Manufacturer Part Number: M30290FAHP#U5A
• Description: IC M16C/29 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/29r

Specifications of M30290FAHP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 27x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
Date
REVISION HISTORY
318-321 • Figure 19.1 I/O Ports (1) to Figure 19.4 I/O Ports (4) are modified
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• Figure 16.3 S00 Register Note is modified
• Figure 16.4 S1D0 Register Reserved bit map modified
• Figure 16.5 S10 Register b7-b6 modified
• Figure 16.7 S4D0 Register Bit reserved map is modified
• 16.5.1 Bit 0: Last Receive Bit (LRB) modified
• 16.5.2 Bit 1: General call detection flag (ADR0) modified, note 1 modified
• 16.5.3 Bit 2: Slave address comparison flag (AAS) modified
• 16.5.5 Bit 4: I
• 16.5.6 Bit 5: Bus Busy Flag (BB) Bit names are modified
• 16.5.8 Bit 7: Communication Mode Select bit (MST) modified
• 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) is modified
• 16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN) is
• 16.11 Stop Condition Generation Method Description added
• 16.13 Address Data Communication modified
CAN Module
• Figure 17.6 C0MCTLj Register RspLock bit’s name changed, note 2 revised
• Figure 17.7 C0CTLR Register Note 4 added, functions partially modified
• Figure 17.8 C0STR Register Note 1 deleted, functions partially modified
• Figure 17.13 C0RECR Register Note 2 deleted, note 1 partially modified
• Figure 17.14 C0TECR Register Note 1 modified, note is relocated
• Figure 17.15 C0TSR Register Note 1 modified
• Figure 17.17 Transition Between Operational Modes Partially modified
• 17.2.3 CAN Sleep Mode Partially deleted
• Table 17.2 Example of Bit-Rate 24-MHz is deleted
• 17.8 Time Stamp Counter and Time Stamp Function Partially deleted
• Figure 17.25 Timing of Receive Data Frame Sequence IF to IFS
• Figure 17.26 Timing of Transmit Sequence IF to IFS
CRC Calculation Circuit
• 18.1 CRC Snoop Description partially added
Programmable I/O Ports
• Note added
• 19.3 Pull-up Control Register 0 to 2 Description partially added
• 19.6 Digital Debounce Function Filter width formula modified
• Figure 19.10 PACR Register Note 1 is modified
• Figure 19.11 NDDR and P17DDR Register Functions modified, notes are added
• Figure 19.12 Functioning of Digital Debounce Filter modified, procedure note
modified
modified
2
C Bus Interface Interrupt Request Bit (PIN) modified
C-10
Description
M16C/29 Hardware Manual
Summary