MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 248

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Signal Descriptions
14-8
A[23:0]
AN[0:3]/AN[W:Z]
AN[52:53]/MA[0:1]
AN[55:56]/
TRIG[1:2]
Breakpoint/
Test mode select
BS[3:0]
CANRX
CANTX
CLKMOD[1:0]
CLKOUT
CS[6:0]
D[31:0]
DDATA[3:0]
DSO/TDO
DSI/TDI
DSCLK/TRST
DRAMW
DTIN[3:0]
DTOUT[3:0]
ECOL
ECRS
Abbreviation
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 14-2. MCF5282 Alphabetical Signal Index
Define the address of external byte, word, longword, and
16-byte burst accesses.
Direct analog input ANn, or multiplexed input ANx.
Direct analog input ANn, or multiplexed output MAn. MAn
selects the output of the external multiplexer.
Direct analog input ANn, or input TRIGn. TRIGn causes one of
the two queues to execute.
Signals a hardware breakpoint in debug mode (BKPT). Provides
information that determines JTAG test operation mode (TMS).
Define the byte lane of data on the data bus.
Controller area network transmit data.
Controller area network transmit data.
Clock mode select
Reflects the system clock.
Programmed for a base address location and for masking
addresses, port size and burst capability indication, wait state
generation, and internal/external termination.
Data bus. Provide the general purpose data path between the
MCU and all other devices.
Display captured processor addresses, data, and breakpoint
status.
Provides single-bit communication for debug module responses
(DSO). Provides serial data port for outputting JTAG logic data
(TDO).
Development serial clock for the serial interface to debug
module (DSCLK). Asynchronously resets the internal JTAG
controller to the test logic reset state (TRST).
Provides single-bit communication for debug module commands
(DSI). Provides serial data port for loading JTAG boundary scan,
bypass, and instruction registers (TDI).
Asserted to signify that a DRAM write cycle is underway.
Negated to indicate a read cycle.
Clock the event counter or provide a trigger to timer value
capture logic.
Pulse or toggle on timer events.
Asserted to indicate a collision.
Note: Not available on MCF5214 and MCF5216
Asserted to indicate that the transmit or receive medium is not
idle.
Note: Not available on MCF5214 and MCF5216
Function
Freescale Semiconductor
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I