MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 468

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

I
For a master receiver to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last
byte. Before the last byte is read, a STOP signal must be generated, as in the following example.
24.4.5
If the master wants the bus after the data transfer, it can signal another START followed by another slave
address without signaling a STOP, as in the following example.
24.4.6
In the slave interrupt service routine, software must poll the I2SR[IAAS] bit to determine if the controller
has received its slave address. If IAAS is set, software must set the transmit/receive mode select bit
(I2CR[MTX]) according to the I2SR[SRW]. Writing to I2CR clears IAAS automatically. The only time
IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred;
interrupts resulting from subsequent data transfers have IAAS cleared. A data transfer can now be initiated
by writing information to I2DR for slave transmits, or read from I2DR in slave-receive mode. A dummy
read of I2DR in slave/receive mode releases I2C_SCL, allowing the master to send data.
In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data. Setting
RXAK means an end-of-data signal from the master receiver, after which software must switch it from
transmitter to receiver mode. Reading I2DR releases I2C_SCL so the master can generate a STOP signal.
24.4.7
If several devices try to engage the bus at the same time, one becomes master. Hardware immediately
switches devices that lose arbitration to slave receive mode. Data output to I2C_SDA stops, but I2C_SCL
continues generating until the end of the byte during which arbitration is lost. An interrupt occurs at the
falling edge of the ninth clock of this transfer with I2SR[IAL] set and I2CR[MSTA] cleared.
If a non-master device tries to transmit or execute a START, hardware inhibits the transmission, clears
MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed
attempt to engage the bus. When considering these cases, slave service routine should first test IAL and
software should clear it if it is set.
24-14
2
C Interface
1. Decrement RXCNT.
2. If last byte (RXCNT = 0) go to step #4.
3. If next to last byte (RXCNT = 1), set I2CR[TXAK] to disable ACK and go to step #5.
4. This is last byte, so clear I2CR[MSTA] to generate a STOP signal.
5. Read data from I2DR.
6. If there is more data to be read (RXCNT ≠ 0), go to step #1 if desired.
1. Generate a repeated START by setting I2CR[RSTA].
2. Transmit the calling address via I2DR.
Generation of Repeated START
Slave Mode
Arbitration Lost
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor