MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 623

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Debug Support
target instruction. The PST can continue with the next instruction before the address has completely
displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured
values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.
30.4
Programming Model
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains 19 registers to support the required functionality. These registers
are also accessible from the processor’s supervisor programming model by executing the WDEBUG
instruction (write only). Thus, the breakpoint hardware in the debug module can be written by the external
development system using the debug serial interface or by the operating system running on the processor
core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically
consistent. Hardware provides a locking mechanism in the CSR to allow the external development system
to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM
commands must not be issued if the device is using the WDEBUG instruction to access debug module
registers or the resulting behavior is undefined.
These registers, shown in
Figure
30-4, are treated as 32-bit quantities, regardless of the number of
implemented bits.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
30-5