M30620FCAFP#U5 Renesas Electronics America, M30620FCAFP#U5 Datasheet - Page 452

• Manufacturer Part Number: M30620FCAFP#U5
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30620FCAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: M16C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: SIM/UART
• On-chip Adc: 10-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A-D Converter
Table 2.7.10. Relationship of the successive comparison register contents and Vref
2.7.11 Method of A-D Conversion (10-bit mode)
Successive approximation register : n
(1) The A-D converter compares the reference voltage (Vref) generated internally based on the
contents of the successive comparison register with the analog input voltage (V
the analog input pin. Each bit of the comparison result is stored in the successive comparison
register until analog-to-digital conversion (successive comparison method) is complete. If a
trigger occurs, the A-D converter carries out the following:
Vref is generated based on the latest content of the successive comparison register. Table
2.7.10 shows the relationship of the successive comparison register contents and Vref. Table
2.7.11 shows how the successive comparison register and Vref vary while A-D conversion is
in progress. Figure 2.7.23 shows theoretical A-D conversion characteristics.
1. Fixes bit 9 of the successive comparison register.
2. Fixes bit 8 of the successive comparison register.
3. Fixes bit 7 through bit 0 of the successive comparison register.
Compares Vref with V
register are “1000000000
Bit 9 of the successive comparison register varies depending on the comparison re-
sult as follows.
Sets bit 8 of the successive comparison register to “1”, then compares Vref with V
Bit 8 of the successive comparison register varies depending on the comparison
result as follows:
Carries out step 2 above on bit 7 through bit 0.
After bit 0 is fixed, the contents of the successive comparison register (conversion
result) are transmitted to A-D register i.
1 to1023
If Vref < V
If Vref > V
If Vref < V
If Vref > V
0
IN
IN
IN
IN
, then “1” is assigned to bit 9.
, then “0” is assigned to bit 9.
, then “1” is assigned to bit 8.
, then “0” is assigned to bit 8.
IN
: [In this instance, the contents of the successive comparison
2
” (default).]
1024
V
REF
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
x
Vref (V)
0
n
–
M16C / 62A Group
V
2048
Mitsubishi microcomputers
REF
IN
) input from
2-133
IN
.