M30620FCAFP#U5 Renesas Electronics America, M30620FCAFP#U5 Datasheet - Page 487

• Manufacturer Part Number: M30620FCAFP#U5
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30620FCAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: M16C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: SIM/UART
• On-chip Adc: 10-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Multiple Interrupts
2-168
Figure 2.14.3. The timing of reflecting the change in the I flag to the interrupt
(2) Interrupt Enable Flag (I flag)
(3) Interrupt Request Bit
(4) Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
When changed by FCLR, FSET, POPC, or LDC instruction
When changed by REIT instruction
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting
this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This
flag is set to “0” after reset.
The content is changed when the I flag is changed causes the acceptance of the interrupt request in
the following timing:
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware.
The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component
bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is
compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher
than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 2.14.1 shows the settings of interrupt priority levels and Table 2.14.2 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
Interrupt request generated
Interrupt request generated
• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the
effect as the REIT instruction is executed.
acceptance of the interrupt is effective as the next instruction is executed.
(If I flag is changed from 0 to 1 by REIT instruction)
(If I flag is changed from 0 to 1 by FSET instruction)
instruction
instruction
Previous
Previous
FSET I
REIT
Determination whether or not to
accept interrupt request
Interrupt sequence
Next instruction
Determination whether or not to
accept interrupt request
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Time
Interrupt sequence
M16C / 62A Group
Mitsubishi microcomputers
Time