UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 541

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SCKA0
(c) Repeat transmission mode
SOA0
In this mode, data stored in the internal buffer RAM is transmitted repeatedly.
Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7
(CSIAE0), bit 6 (ATE0), bit 5 (ATM0), and bit 3 (TXEA0) of serial operation mode specification register 0
(CSIMA0) are set to 1.
Unlike the automatic transmission mode, after the number of setting bytes has been transmitted, the interrupt
request flag (ACSIIF) is not set, automatic data transfer address count register 0 (ADTC0) is reset to 0, and
the internal buffer RAM contents are transmitted again.
When a reception operation, busy control and strobe control are not performed, the SIA0/P143,
BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as ordinary I/O port pins.
The example of the repeat transmission mode operation timing is shown in Figure 17-19, and the operation
flowchart in Figure 17-20.
Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM after
D7 D6 D5 D4 D3 D2 D1 D0
Figure 17-19. Example of Repeat Transmission Mode Operation Timing
2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by
the transmission of one byte, the interval is included in the period up to the next
transmission.
processing, the interval is dependent upon automatic data transfer interval specification
register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0, BUSYE0) of serial status
register 0 (CSIS0) (see (5) Automatic transmit/receive interval time).
serial interface CSIA0 during the interval period, the interval time specified by automatic
data transfer interval specification register 0 (ADTI0) may be extended.
As the buffer RAM read is performed at the same time as CPU
Interval
D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 17 SERIAL INTERFACE CSIA0
Interval
D7 D6 D5
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