UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 962

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Serial
interface
CSI10,
CSI11
Serial
interface
CSIA0
Function
SOTB1n: Transmit
buffer register 1n
CSIM10: Serial
operation mode
register 10
CSIC10: Serial clock
selection register 10
CSIC11: Serial clock
selection register 11
3-wire serial I/O mode Take relationship with the other party of communication when setting the port
Communication
operation
SO1n output
SIOA0: Serial I/O shift
register 0
CSIMA0:
Serial operation mode
specification register 0
CSIS0: Serial status
register 0
CSIT0: Serial trigger
register 0
Details of Function
Do not access SOTB1n when CSOT1n = 1 (during serial communication).
In the slave mode, transmission/reception is started when data is written to
SOTB11 with a low level input to the SSI11 pin. For details on the
transmission/reception operation, see 16.4.2 (2) Communication operation.
Be sure to clear bit 5 to 0.
Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
To use P10/SCK10/T
the default status (00H).
The phase type of the data clock is type 1 after reset.
Do not write to CSIC11 while CSIE11 = 1 (operation enabled).
To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the
default status (00H).
The phase type of the data clock is type 1 after reset.
mode register and port register.
Do not access the control register and data register when CSOT1n = 1 (during
serial communication).
When using serial interface CSI11, wait for the duration of at least one clock before
the clock operation is started to change the level of the SSI11 pin in the slave
mode; otherwise, malfunctioning may occur.
If a value is written to CSIE1n, TRMD1n, DAP1n, and DIR1n, the output value of
SO1n changes.
A communication operation is started by writing to SIOA0. Consequently, when
transmission is disabled (bit 3 (TXEA0) of CSIMA0 = 0), write dummy data to the
SIOA0 register to start the communication operation, and then perform a receive
operation.
Do not write data to SIOA0 while the automatic transmit/receive function is
operating.
When CSIAE0 = 0, the buffer RAM cannot be accessed.
When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note
above are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set
the initialized registers.
When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not
guaranteed that the value of the buffer RAM will be retained.
Be sure to clear bit 7 to 0.
During transfer (TSF0 = 1), rewriting serial operation mode specification register 0
(CSIMA0), serial status register 0 (CSIS0), divisor selection register 0 (BRGCA0),
automatic data transfer address point specification register 0 (ADTP0), automatic
data transfer interval specification register 0 (ADTI0), and serial I/O shift register 0
(SIOA0) are prohibited. However, these registers can be read and re-written to the
same value. In addition, the buffer RAM can be rewritten during transfer.
Even if ATSTP0 or ATSTA0 is set to 1, automatic transfer cannot be
started/stopped until 1-byte transfer is complete.
ATSTP0 and ATSTA0 change to 0 automatically after the interrupt signal INTACSI
is generated.
After automatic data transfer is stopped, the data address when the transfer
stopped is stored in automatic data transfer address count register 0 (ADTC0).
However, since no function to restart automatic data transfer is incorporated, when
transfer is stopped by setting ATSTP0 = 1, start automatic data transfer by setting
ATSTA0 to 1 after re-setting the registers.
X
D0 and P12/SO10 as general-purpose ports, set CSIC10 in
Cautions
APPENDIX D LIST OF CAUTIONS
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