UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 584

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.15 Cautions
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0
(2) When STCEN = 1
(3) If other I
(4) Determine the transfer clock frequency by using SMC0, CL01, CL00 bits (bits 3, 1, and 0 of IICL0 register), and
Immediately after I
1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has
been detected to a master device communication mode, first generate a stop condition to release the bus, then
perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock selection register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
Immediately after I
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0
(IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications.
If I
low and the SCL0 pin is high, the macro of I
condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this
interferes with other I
<1> Clear bit 4 (SPIE0) of IICC0 register to 0 to disable generation of an interrupt request signal (INTIIC0) when
<2> Set bit 7 (IICE0) of IICC0 register to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 register to 1 before ACK is returned (4 to 80 clocks after setting IICE0 bit to 1), to
CLX0 bit (bit 0 of IICX0 register) before enabling the operation (IICE0 = 1). To change the transfer clock frequency,
clear IICE0 bit to 0 once.
2
C operation is enabled and the device participates in communication already in progress when the SDA0 pin is
the stop condition is detected.
forcibly disable detection.
2
C communications are already in progress
2
C operation is enabled (IICE0 = 1), the bus communication status (IICBSY flag (bit 6 of IICF0) =
2
C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
2
C communications. To avoid this, start I
CL01
0
0
1
1
Table 18-7. Wait Periods
CL00
2
0
1
0
1
C recognizes that the SDA0 pin has gone low (detects a start
6 clocks
6 clocks
12 clocks
3 clocks
Wait Period
2
C in the following sequence.
CHAPTER 18 SERIAL INTERFACE IIC0
2
C.
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