UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 546

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SCKA0
BUSY0
ACSIIF
Figure 17-24. Example of Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1)
SOA0
TSF0
SIA0
(active-high)
Remark
When the busy signal becomes inactive, waiting is released.
transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock.
Because the busy signal is asynchronous with the serial clock, it takes up to 1 clock until the busy signal is
sampled, even if made inactive by the slave. It takes 0.5 clock until data transfer is started after the busy
signal was sampled.
To accurately release the waiting, keep the busy signal inactive at the slave side, until SCKA0 falls.
Figure 17-25 shows the example of the timing of the busy signal and releasing the waiting. This figure shows
an example in which the busy signal is active as soon as transmission/reception has been started.
SCKA0
BUSY0
SOA0
SIA0
D7
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0
ACSIIF: Interrupt request flag
TSF0:
Figure 17-25. Busy Signal and Wait Release (When BUSYLV0 = 1)
D7
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0
Bit 0 of serial status register 0 (CSIS0)
If made inactive
immediately after
sampled
Wait
Wait
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 17 SERIAL INTERFACE CSIA0
Busy input released
Busy input valid
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1.5 clocks (MAX.)
Busy input released
Busy input valid
If the sampled busy signal is inactive,
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