UPD78F0500MC-5A4-A Renesas Electronics America, UPD78F0500MC-5A4-A Datasheet - Page 950

• Manufacturer Part Number: UPD78F0500MC-5A4-A
• Description: MCU 8BIT FLASH SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500MC-5A4-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
CPU clock
16-bit
timer/event
counters 00,
01
Function
TM0n: 16-bit timer
counter 0n
CR00n, CR01n:
16-bit timer
capture/compare
registers 00n, 01n
TMC0n: 16-bit
timer mode
control register 0n
CRC0n: Capture/
compare control
register 0n
TOC0n: 16-bit
timer output
control register 0n
Details of
Function
−
−
<1> Set TOC0n4 and TOC0n1 to 1.
<2> Set only TOE0n to 1.
<3> Set either of LVS0n or LVR0n to 1.
Set the clock after the supply voltage has reached the operable voltage of the clock
to be set (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE
PRODUCTS : T
Selection of the main system clock cycle division factor (PCC0 to PCC2) and
switchover from the main system clock to the subsystem clock (changing CSS from
0 to 1) should not be set simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock
cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to
the main system clock (changing CSS from 1 to 0).
When switching the internal high-speed oscillation clock to the high-speed system
clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be
changed only once after a reset release.
Do not rewrite MCM0 when the CPU clock operates with the subsystem clock.
The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at
the same time, and the valid edge of TI011 and timer output (TO01) cannot be used
for the P06 pin at the same time. Select either of the functions.
If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control
register 0n (TMC0n) to 00 and input of the capture trigger conflict, then the
captured data is undefined.
To change the mode from the capture mode to the comparison mode, first clear the
TMC0n3 and TMC0n2 bits to 00, and then change the setting. A value that has
been once captured remains stored in CR00n unless the device is reset. If the
mode has been changed to the comparison mode, be sure to set a comparison
value.
Even if TM0n is read, the value is not captured by CR01n.
CR00n does not perform the capture operation when it is set in the comparison
mode, even if a capture trigger is input to it.
CR01n does not perform the capture operation when it is set in the comparison
mode, even if a capture trigger is input to it.
To capture the count value of the TM0n register to the CR00n register by using the
phase reverse to that input to the TI00n pin, the interrupt request signal
(INTTM00n) is not generated after the value has been captured. If the valid edge is
detected on the TI01n pin during this operation, the capture operation is not
performed but the INTTM00n signal is generated as an external interrupt signal. To
not use the external interrupt, mask the INTTM00n signal.
16-bit timer/event counter 0n starts operation at the moment TMC0n2 and TMC0n3
are set to values other than 00 (operation stop mode), respectively. Set TMC0n2
and TMC0n3 to 00 to stop the operation.
To ensure that the capture operation is performed properly, the capture trigger
requires a pulse two cycles longer than the count clock selected by prescaler mode
register 0n (PRM0n).
Be sure to set TOC0n using the following procedure.
A
= • 40 to +125°C)).
Cautions
APPENDIX D LIST OF CAUTIONS
pp. 260,
261, 263
p. 266
p. 267
p. 267
p. 272
p. 272
p. 272
p. 273
p. 274
p. 274
p. 276
p. 277
pp. 280,
281
p. 282
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