UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 153

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
5.2
5.2.1
5.2.2
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
The pins used to connect an external device are listed in the table below.
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Caution When a write access is performed to the internal ROM area, address, data, and control signals are
For the pin status of the V850ES/JF3-L in each operation mode, see 2.2 Pin States.
AD0 to AD15
A16, A17
WAIT
CLKOUT
WR0, WR1
RD
ASTB
HLDRQ
HLDAK
Bus Control Pins
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
Pin status in each operation mode
Bus Control Pin
Table 5-2. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
activated in the same way as access to the external memory area.
Address/data bus (AD15 to AD0)
Address bus (A17, A16)
Control signal
Bus Control Pin
PDL0 to PDL15
PDH0, PDH1
PCM0
PCM1
PCT0, PCT1
PCT4
PCT6
PCM3
PCM2
Alternate-Function Pin
Table 5-1. Bus Control Pins
Undefined
Low level
Inactive
Output
Output
Output
Output
Output
Output
Internal ROM/RAM
Input
Input
I/O
I/O
Address/data bus
Address bus
External wait control
Internal system clock
Write strobe signal
Read strobe signal
Address strobe signal
Bus hold control
Multiplexed Bus Mode
CHAPTER 5 BUS CONTROL FUNCTION
Undefined
Undefined
Inactive
Peripheral I/O
Function
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