UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 9

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 136
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 158
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ................................................................ 172
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.1
6.2
6.3
6.4
6.5
7.1
7.2
7.3
7.4
7.5
Block Diagrams........................................................................................................................96
Port Register Settings When Alternate Function Is Used ................................................ 124
Cautions ................................................................................................................................ 131
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
Features................................................................................................................................. 136
Bus Control Pins................................................................................................................... 137
5.2.1
5.2.2
Memory Block Function....................................................................................................... 138
Bus Access ........................................................................................................................... 139
5.4.1
5.4.2
5.4.3
Wait Function ........................................................................................................................ 147
5.5.1
5.5.2
5.5.3
5.5.4
Idle State Insertion Function ............................................................................................... 151
Bus Hold Function................................................................................................................ 152
5.7.1
5.7.2
5.7.3
Bus Priority ........................................................................................................................... 154
Bus Timing ............................................................................................................................ 155
Overview................................................................................................................................ 158
Configuration ........................................................................................................................ 159
Registers ............................................................................................................................... 161
Operation............................................................................................................................... 166
6.4.1
6.4.2
PLL Function......................................................................................................................... 167
6.5.1
6.5.2
6.5.3
Overview................................................................................................................................ 172
Functions............................................................................................................................... 172
Configuration ........................................................................................................................ 173
Registers ............................................................................................................................... 175
Operation............................................................................................................................... 187
7.5.1
Cautions on setting port pins ...................................................................................................131
Cautions on bit manipulation instruction for port n register (Pn)...............................................134
Cautions on on-chip debug pins...............................................................................................135
Cautions on P05/INTP2/DRST pin...........................................................................................135
Cautions on P10 and P53 pins when power is turned on.........................................................135
Hysteresis characteristics ........................................................................................................135
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............137
Pin status in each operation mode...........................................................................................137
Number of clocks for access....................................................................................................139
Bus size setting function ..........................................................................................................139
Access by bus size ..................................................................................................................140
Programmable wait function ....................................................................................................147
External wait function...............................................................................................................148
Relationship between programmable wait and external wait ...................................................149
Programmable address wait function.......................................................................................150
Functional outline.....................................................................................................................152
Bus hold procedure..................................................................................................................153
Operation in power save mode ................................................................................................153
Operation of each clock ...........................................................................................................166
Clock output function ...............................................................................................................166
Overview..................................................................................................................................167
Registers..................................................................................................................................167
Usage ......................................................................................................................................171
Interval timer mode (TPnMD2 to TPnMD0 bits = 000) .............................................................188