UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 670

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
21.2 Registers
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
(1) Power save control register (PSC)
The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to
specify the STOP mode. This register is a special register that can be written only by the special sequence
combinations (see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode
Cautions 1. Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1
After reset: 00H
PSC
NMI1M
NMI0M
INTM
2. Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is
3. If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set
STP
0
1
0
1
0
1
0
1
7
0
and PSMR.PSM0 bits and then set the STP bit.
released.
to 1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an
unmasked
IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt
request signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1.
Standby mode release by INTWDT2 signal enabled
Standby mode release by INTWDT2 signal disabled
Standby mode release by NMI pin input enabled
Standby mode release by NMI pin input disabled
Standby mode release by maskable interrupt request signal enabled
Standby mode release by maskable interrupt request signal disabled
Normal mode
Standby mode
NMI1M
R/W
<6>
Standby mode release control via maskable interrupt request signal
Standby mode release control upon occurrence of INTWDT2 signal
interrupt
Address: FFFFF1FEH
NMI0M
<5>
Standby mode release control by NMI pin input
INTM
request
<4>
Standby mode
signal
3
0
Note
setting
being
CHAPTER 21 STANDBY FUNCTION
2
0
held
STP
<1>
pending
0
0
when
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the