UPD70F3735GK-GAK-AX Renesas Electronics America, UPD70F3735GK-GAK-AX Datasheet - Page 560

• Manufacturer Part Number: UPD70F3735GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3735GK-GAK-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JF3-L
17.6.7 Wait state cancellation method
between the SDA0n line change timing and IICn register write timing may result in the data output to the SDA0n line may
be incorrect.
enabling wait state to be cancelled.
exited, enabling wait state to be cancelled.
R01UH0017EJ0400 Rev.4.00
Sep 30, 2010
In the case of I
• By writing data to the IICn register
• By setting the IICCn.WRELn bit to 1 (wait state cancellation)
• By setting the IICCn.STTn bit to 1 (start condition generation)
• By setting the IICCn.SPTn bit to 1 (stop condition generation)
If any of these wait state cancellation actions is performed, I
When canceling wait state and sending data (including address), write data to the IICn register.
To receive data after canceling wait state, or to complete data transmission, set the WRELn bit to 1.
To generate a restart condition after canceling wait state, set the STTn bit to 1.
To generate a stop condition after canceling wait state, set the SPTn bit to 1.
Execute cancellation only once for each wait state.
For example, if data is written to the IICn register following wait state cancellation by setting the WRELn bit to 1, conflict
Even in other operations, if communication is stopped halfway, clearing the IICCn.IICEn bit to 0 will stop communication,
If the I
2
C bus dead-locks due to noise, etc., setting the IICCn.LRELn bit to 1 causes the communication operation to be
2
C0n, wait state can be canceled normally in the following ways (n = 0, 1).
2
C0n will cancel wait state and restart communication.
CAPTER 17 I
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2
C BUS