UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 120

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(6) Oscillation stabilization time select register (OSTS)
118
This register is used to select the high-speed system clock oscillation stabilization wait time when STOP mode is
released.
The wait time set by OSTS is valid only after STOP mode is released with the high-speed system clock selected
as CPU clock. After STOP mode is released with internal oscillation clock selected as CPU clock, the oscillation
stabilization time must be confirmed by OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Address: FFA4H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the high-speed system clock is used as the CPU
Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
1
1
After reset: 05H
Other than above
2. Before setting OSTS, confirm with OSTC that the desired oscillation stabilization
3. If the STOP mode is entered and then released while the internal oscillation
4. The wait time when STOP mode is released does not include the time after STOP
XP
: High-speed system clock oscillation frequency
clock, set OSTS before executing a STOP instruction.
time has elapsed.
clock is being used as the CPU clock, set the oscillation stabilization time as
follows.
The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
OSTS1
6
0
0
1
1
0
0
X1 pin voltage
waveform
Desired OSTC oscillation stabilization time
set by OSTS
R/W
CHAPTER 5 CLOCK GENERATOR
OSTS0
User’s Manual U16899EJ3V0UD
5
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
Setting prohibited
11
13
14
15
16
/f
/f
/f
/f
/f
XP
XP
XP
XP
XP
4
0
a
Oscillation stabilization time selection
3
0
204.8 s
819.2 s
1.64 ms
3.27 ms
6.55 ms
f
XP
OSTS2
= 10 MHz
2
Oscillation stabilization time
OSTS1
128 s
512 s
1.02 ms
2.04 ms
4.09 ms
1
f
XP
= 16 MHz
OSTS0
0