UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 473

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16-bit
operation
Multiply/
divide
Increment/
decrement
Rotate
BCD
adjustment
Bit
manipulate
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
ADDW
SUBW
CMPW
MULU
DIVUW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
ROR4
ROL4
ADJBA
ADJBS
MOV1
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
AX, #word
AX, #word
AX, #word
X
C
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
[HL]
[HL]
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Operands
CHAPTER 28 INSTRUCTION SET
User’s Manual U16899EJ3V0UD
Bytes
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
2
2
2
2
3
3
2
3
2
3
3
2
3
2
Note 1
16
25
10
10
6
6
6
2
4
2
4
4
4
2
2
2
2
4
4
6
4
6
6
4
6
Clocks
Note 2
12
12
6
6
7
7
7
7
8
8
8
8
AX, CY
AX, CY
AX
AX
AX (Quotient), C (Remainder)
r
(saddr)
r
(saddr)
rp
rp
(CY, A
(CY, A
(CY
(CY
A
(HL)
A
(HL)
Decimal Adjust Accumulator after Addition
Decimal Adjust Accumulator after Subtract
CY
CY
CY
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
3
3
0
0
r + 1
r
3
7
word
rp + 1
rp
A
7
0
0
4
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
A
A
1
CY
(HL)
(HL)
0
7
CY
, A
, A
1
X
(saddr) + 1
(saddr)
AX + word
AX
A
A
CY
(HL)
(HL)
CY
0
7
7
0
3
7
CPU
, A
, A
CY
4
0
7
3
, (HL)
m
m + 1
, (HL)
word
) selected by the processor clock
CY, A
CY, A
Operation
4
0
1
1
3
7
m
m + 1
A
A
0
4
m
m
1
)
)
A
A
1 time
1 time
3
A
A
3
m
m
0
0
)
)
,
,
AX
1 time
1 time
C
Z AC CY
Flag
471