UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 284

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

282
1. Stop bit length: 1
2. Stop bit length: 2
(c) Transmission
The T
register 0 (ASIM0) is set to 1.
Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity
bit, and stop bit are automatically appended to the data.
When transmission is started, the start bit is output from the T
order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are
appended and a transmission completion interrupt request (INTST0) is generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 13-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
T
T
X
X
D0 (output)
D0 (output)
X
INTST0
INTST0
D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode
transmission completion interrupt signal (INTST0) is generated.
Figure 13-8. Transmission Completion Interrupt Request Timing
Start
Start
CHAPTER 13 SERIAL INTERFACE UART0
D0
D0
If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled.
User’s Manual U16899EJ3V0UD
D1
D1
D2
D2
D6
D6
X
D0 pin, followed by the rest of the data in
D7
D7
Parity
Parity
Stop
Stop