UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 427

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
25.3 Register Controlling ROM Correction
CORCN
The ROM correction is controlled by the correction control register (CORCN).
(1) Correction control register (CORCN)
Symbol
Note Do not set bits 0 and 2 to 1.
This register controls whether or not the correction branch request signal is generated when the fetch address
matches the correction address set in correction address registers 0 and 1. The correction control register
consists of correction enable flags (COREN0, COREN1) and correction status flags (CORST0, CORST1). The
correction enable flags enable or disable the comparator match detection signal, and correction status flags
show the values are matched.
CORCN is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CORCN to 00H.
Clear CORST0 and CORST1 using software.
0
7
0
6
0
5
Figure 25-3. Format of Correction Control Register
0
4
COREN1 CORST1 COREN0 CORST0
<3>
CHAPTER 25 ROM CORRECTION
<2>
User’s Manual U16899EJ3V0UD
<1>
<0>
COREN0
CORST0
CORST1
COREN1
0
1
0
1
1
0
1
0
Address
FF8AH
Disabled
Enabled
Enabled
Not detected
Detected
Not detected
Detected
Disabled
Correction Address Register 1 and Fetch Address Match Detection
Correction Address Register 0 and Fetch Address Match Detection
Correction Address Register 0 and Fetch Address
Correction Address Register 1 and Fetch Address
After reset
00H
Match Detection Control
Match Detection Control
R/W
R/W
Note
425

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