UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 236

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOPn1 pin.
After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a
trigger is generated again while the one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTPnCC1
is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
trigger.
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When the TPnCE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts after its
The valid edge of an external trigger input or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the
Remark
External trigger input
(only when software
INTTPnCC0 signal
INTTPnCC1 signal
TPnCCR0 register
TPnCCR1 register
Output delay period = (Set value of TPnCCR1 register) × Count clock cycle
Active level width = (Set value of TPnCCR0 register − Set value of TPnCCR1 register + 1) × Count clock cycle
TOPn1 pin output
TOPn0 pin output
(TIPn0 pin input)
trigger is used)
16-bit counter
TPnCE bit
n = 0 to 2, 5
FFFFH
0000H
Figure 7-21. Basic Timing in One-Shot Pulse Output Mode
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Delay
(D
D
1
1
)
Preliminary User’s Manual U18952EJ1V0UD
Active
level width
(D
D
0
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
D
D
0
0
1
0
− D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
− D
1
+ 1)