UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 696

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

696
Item
LVI
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP2, TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
Cautions 1. Following the store instruction to the PSC register for setting the sub-IDLE mode/low-voltage
Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
Be sure to observe the above sequence.
For the setting of the subclock operation mode, see 21.7.1 Setting and operation status.
2. To realize low power consumption, stop the A/D and D/A converters before shifting to the sub-IDLE
2. If the sub-IDLE mode/low-voltage sub-IDLE mode is set while an unmasked interrupt request
mode.
Setting of Sub-IDLE Mode
sub-IDLE mode, insert the five or more NOP instructions.
signal is being held pending, the sub-IDLE mode/low-voltage sub-IDLE mode is then released
immediately by the pending interrupt request.
CSIB0 to CSIB2
I
UARTA0 to UARTA2
2
C00, I
2
C01
Table 21-13. Operating Status in Sub-IDLE Mode
Operable
Oscillates
Oscillation enabled
Operable
Stops operation
Stops operation
Stops operation (but standby mode release is possible)
Stops operation
Stops operation
Operable when f
Operable
Operable when f
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 2)
Stops operation
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
Holds operation (conversion result held)
Holds operation (output held)
Stops operation (output held)
Operable
Stops operation
See 2.2 Pin States (same operation status as IDLE1 and IDLE2 modes).
Retains status before sub-IDLE mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the sub-IDLE mode was set.
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18952EJ1V0UD
When Main Clock Is Oscillating
R
R
/8 or f
or f
XT
XT
is selected as the count clock
is selected as the count clock
Note 2
Operating Status
Note 2
Stops operation
Operable when f
count clock
When Main Clock Is Stopped
Note 1
XT
is selected as the