UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 695

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.8 Sub-IDLE Mode/Low-Voltage Sub-IDLE Mode
21.8.1 Setting and operation status
bit to 1 in the subclock operation mode. The low-voltage sub-IDLE mode is set by setting the PSMR.PSM1 and
PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 after setting the REGOVL0 register to 02H in the
subclock operation mode.
chip peripheral functions is stopped.
retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions
that can operate with the subclock or an external clock, continue operating. In the subclock operation mode, CSIBn
and UARTA0, which can operate with the external clock, continue operating. In the low-voltage subclock operation
mode, stop supply of the external clock input to CSIBn and UARTA0 (n = 0 to 2).
can reduce the power consumption more than the subclock operation mode.
level as low as that in the STOP mode. The power consumption decreases further in the low-voltage sub-IDLE mode
because the voltage of the regulator is lowered.
low-voltage sub-IDLE mode.
The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP
In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other on-
As a result, program execution stops and the contents of the internal RAM before the sub-IDLE mode was set are
Because the sub-IDLE mode stops operation of the CPU, flash memory, and other on-chip peripheral functions, it
If the sub-IDLE mode is set after the main clock has been stopped, the current consumption can be reduced to a
Table 21-13 shows the operating status in the sub-IDLE mode and Table 21-14 shows the operating status in the
Be sure to set the low-voltage sub-IDLE mode in the following procedure.
(1) Procedure for setting “subclock operation mode” → “low-voltage subclock operation mode” → “low-
voltage sub-IDLE mode”
Make the following settings in the subclock operation mode.
<1> Stop the main clock and PLL.
<2> Stop the functions that are specified to be stopped in Table 21-14 Operating Status in Low-Voltage
<3> Disable the DMA operation (if the DMA operation is enabled).
<4> • Disable the maskable interrupt by the DI instruction.
<5> Write C9H (enabling data) to the REGPR register.
<6> Write 02H to the REGOVL0 register.
<7> Write 00H (protection data) to the REGPR register.
<8> As necessary, enable the maskable interrupt, NMI interrupt, or INTWDT2 interrupt by the EI instruction
<9> Set the sub-IDLE mode.
Sub-IDLE Mode.
Be especially sure to stop the following functions, because they are signals from external sources.
• Stop SCKBn input clock when the SCKBn input clock to CSIBn is selected (n = 0 to 2).
• Stop ASCKA0 input clock when the ASCKA0 input clock to UARTA0 is selected.
• Disable the NMI interrupt (INTF02 = 0, INTR02 = 0).
• Create a status in which the INTWDT2 signal is not generated (set a status in which the INTWDT2
At this time, the output voltage of the regulator is at the low level, decreasing the power consumption to
an extremely low level.
(restore the settings in step <4>).
signal is not generated immediately after watchdog timer 2 has been cleared).
PSMR.PSM1, PSMR.PSM0 bits = 00 or 10
PSC.STP bit = 1
CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U18952EJ1V0UD
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