UPD70F3736GK-GAK-AX Renesas Electronics America, UPD70F3736GK-GAK-AX Datasheet - Page 727

• Manufacturer Part Number: UPD70F3736GK-GAK-AX
• Description: MCU 32BIT V850ES/JX3-L 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3736GK-GAK-AX

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 20MHz
• Number Of I /o: 66
• Core Processor: RISC
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b, D/A 1x8b
• Oscillator Type: Internal
• Peripherals: DMA, LVD, PWM, WDT
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This 8-bit data is used to set the oscillation stabilization time that elapses after the reset status is released. After the
reset status is released, the oscillation stabilization time is ensured to pass by this set value.
The option byte is stored in address 000007AH of the internal flash memory (internal ROM area) as 8-bit data.
When writing a program to the V850ES/JF3-L, be sure to set the option data in the program at address 000007AH.
The data in this area cannot be rewritten during program execution.
Remark The wait time after releasing the STOP mode or IDLE2 mode is set by the OSTS register. For details
Cautions 1. The oscillation stabilization time shown above is longer than the theoretical value because
of the OSTS register, see 21.2 (3) Oscillation stabilization time select register (OSTS).
2. Be sure to select an oscillation stabilization time (theoretical value) of 400
the overhead time since power application is taken into consideration.
oscillation stabilization time is the time shown above, plus up to 260
it is set to less than 400
be guaranteed.
Address: 0000007AH
OSTS2
RES
0
0
0
0
0
1
1
1
1
OSTS1
RES
0
0
0
1
1
0
0
1
1
CHAPTER 27 OPTION BYTE
Preliminary User’s Manual U18952EJ1V0UD
OSTS0
RES
μ
0
0
1
0
1
0
1
0
1
s, the internal status becomes unstable and the operation cannot
Selection of oscillation stabilization time (theoretical value)
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
16
/f
/f
/f
/f
/f
/f
/f
/f
0
X
X
X
X
X
X
X
X
1.638 ms
3.277 ms
6.554 ms
13.11 ms
26.21 ms
26.21 ms
409.6 s
819.2 s
2.5 MHz
0
μ
μ
RESOSTS2 RESOSTS1 RESOSTS0
Setting prohibited
409.6 s
819.2 s
1.638 ms
3.277 ms
6.554 ms
13.11 ms
13.11 ms
5 MHz
f
X
μ
μ
Setting prohibited
Setting prohibited
409.6 s
819.2 s
1.638 ms
3.277 ms
6.554 ms
6.554 ms
10 MHz
μ
μ
μ
s.
μ
s or longer. If
The actual
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