SAK-TC1197-512F180E AC Infineon Technologies, SAK-TC1197-512F180E AC Datasheet - Page 154

• Manufacturer Part Number: SAK-TC1197-512F180E AC
• Description: IC MCU 32BIT 4MB FLASH BGA416-10
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAK-TC1197-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4) Applicable for input pins TESTMODE and TRST.
5)
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
9) The duration of the boot time is defined between the following events:
Figure 25
Data Sheet
TESTMODE
f
user instruction has entered the CPU and its processing starts.
1. Hardware reset: the falling edge of a short ESR0 pulse and the moment when the first user instruction has
entered
SCU_RSTCNTCON.RELSA ×
If the ESR0 pulse is longer than SCU_RSTCNTCON.RELSA ×
the boot time (ESR0 falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
FPI
HWCFG
PORST
=
VDDP
TRST
ESR0
Pads
VDD
f
CPU
V
D D PPA
/2
the
Power, Pad and Reset Timing
Pad-state undefined
Tri-state or pull device active
As programmed
CPU
t
POA
t
POA
and
t
hd
t
PIP
T
t
POH
its
FPI
t
t
HDH
PI
.
processing
t
PIP
t
PI
150
starts,
t
hd
t
PIP
if
t
POH
t
t
T
HDH
PI
FPI
the
, only the time beyond should be added to
ESR0
t
t
HDH
PI
Electrical Parameters
pulse
t
PI
V
D D
-12%
is
V1.1, 2009-05
shorter
V
TC1197
D D P
V
reset_beh2
D D PPA
-12%
than