SAK-TC1197-512F180E AC Infineon Technologies, SAK-TC1197-512F180E AC Datasheet - Page 156

• Manufacturer Part Number: SAK-TC1197-512F180E AC
• Description: IC MCU 32BIT 4MB FLASH BGA416-10
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAK-TC1197-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

With rising number
of
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency
Figure 26
Figure 26
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
Data Sheet
m
D
m
±10.0
that is defined by the K2-factor of the PLL. Beyond this value of
±4.0
±2.0
±0.0
±8.0
±7.0
±6.0
±1.0
not exceed
applications with many pins with high loads, driver strengths and toggle rates the
specified jitter values could be exceeded.
V
V
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V
V
frequencies above 300 KHz.
DDOSC3
PP
DDOSC
PP
ns
0
= 100 mV for noise frequencies below 300 KHz and
= 100 mV for noise frequencies below 300 KHz and
f
gives the jitter curves for several K2 /
D
m
K2
LMB
m
= Max. jitter
= Number of consecutive f
= K2-divider of PLL
at pin F26 and
Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies
at pin E26 and
results in a higher absolute maximum jitter value.
C
m
20
L
of clock cycles the maximum jitter increases linearly up to a value
= 20 pF with the maximum driver and sharp edge. In case of
f
LMB
= 50 MHz (K2 = 8)
V
V
f
40
LMB
SSOSC
SSOSC
= 50 MHz (K2 = 16)
f
LMB
f
LMB
LMB
at pin F25, is limited to a peak-to-peak voltage of
at pin F25, is limited to a peak-to-peak voltage of
= 100 MHz (K2 = 4)
= 100 MHz (K2 = 8)
periods
f
LMB
60
152
f
f
LMB
LMB
80
= 150 MHz (K2 = 4)
combinations.
f
LMB
= 180 MHz (K2 = 4)
100
Electrical Parameters
V
V
PP
PP
TC1797_PLL_JITT_M
= 40 mV for noise
= 40 mV for noise
m
120
the maximum
V1.1, 2009-05
TC1197
o
m
o