SAK-TC1197-512F180E AC Infineon Technologies, SAK-TC1197-512F180E AC Datasheet - Page 58

• Manufacturer Part Number: SAK-TC1197-512F180E AC
• Description: IC MCU 32BIT 4MB FLASH BGA416-10
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAK-TC1197-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.6.1
The classic software debug approach (start/stop, single-stepping) is supported by
several features labelled “OCDS Level 1”:
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2.6.2
For detailed tracing of the system’s behavior a pin-compatible Emulation Device will be
available.
2.6.3
Two main use cases are catered for by resources in addition the OCDS Level 1
infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling:
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1) The OCDS L2 interface of AudoNG is not available.
Data Sheet
Run/stop and single-step execution independently for TriCore and PCP.
Means to request all kinds of reset without usage of sideband pins.
Halt-after-Reset for repeatable debug sessions.
Different Boot modes to use application software not yet programmed to the Flash.
A total of four hardware breakpoints for the TriCore based on instruction address,
data address or combination of both.
Unlimited number of software breakpoints (DEBUG instruction) for TriCore and PCP.
Debug event generated by access to a specific address via the system bus.
Tool access to all SFRs and internal memories independent of the Cores.
Two central Break Switches to collect debug events from all modules (TriCore, PCP,
DMA, BCU, break input pins) and distribute them selectively to breakable modules
(TriCore, PCP, break output pins).
Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals)
instead if breaking them as reaction to a debug event.
Dedicated interrupt resources to handle debug events inside TriCore (breakpoint
trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing
Monitor programs.
Access to all OCDS Level 1 resources also for TriCore and PCP themselves for
debug tools integrated into the application code.
Triggered Transfer of data in response to a debug event; if target is programmed to
be a device interface simple variable tracing can be done.
In depth performance analysis and profiling support given by the Emulation Device
through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit,
wait state, interrupt accepted).
8 KB SRAM for Overlay.
Can be split into up to 16 blocks which can overlay independent regions of on-chip
Data Flash.
1)
On-Chip Debug Support
Real Time Trace
Calibration Support
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Introduction
V1.1, 2009-05
TC1197