Z8F042AHH020SC00TR Zilog, Z8F042AHH020SC00TR Datasheet - Page 114

• Manufacturer Part Number: Z8F042AHH020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHH020SC00T

PS022825-0908
1
0
Idle State
of Line
Clear To Send (CTS) Operation
MULTIPROCESSOR (9-bit) Mode
Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format
3. Clears the UART Receiver interrupt in the applicable Interrupt Request register.
4. Executes the IRET instruction to return from the interrupt-service routine and await
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow
control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sam-
pled one system clock before beginning any new character transmission. To delay trans-
mission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character trans-
missions, this action is typically performed during Stop Bit transmission. If CTS deasserts
in the middle of a character transmission, the current character is sent completely.
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for selec-
tive communication when a number of processors share a common UART bus. In MULTI-
PROCESSOR mode (also referred to as 9-bit mode), the multiprocessor bit (
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as displayed in
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the
Multiprocessor control bit. The UART Control 1 and Status 1 registers provide MULTI-
PROCESSOR (9-bit) mode control and status information. If an automatic address match-
ing scheme is enabled, the UART Address Compare register holds the network address of
the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed
to it. The determination of whether a frame of data is addressed to the UART can be made
in hardware, software or some combination of the two, depending on the multiprocessor
Start
more data.
Bit0
lsb
Bit1
Figure
Bit2
13. The character format is:
Bit3
Data Field
Bit4
Bit5
Universal Asynchronous Receiver/Transmitter
Bit6
Z8 Encore! XP
msb
Bit7
Product Specification
MP
®
F082A Series
1
Stop Bit(s)
MP
2
) is
103