Z8F042AHH020SC00TR Zilog, Z8F042AHH020SC00TR Datasheet - Page 88

• Manufacturer Part Number: Z8F042AHH020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHH020SC00T

PS022825-0908
5. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
7. Configure the associated GPIO port pin for the Timer Output and Timer Output
8. Write to the Timer Control register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
If an initial starting value other than
registers, the ONE-SHOT mode equation determines the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre-
sented by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the appropriate exter-
nal Timer Input transition occurs. The Capture count value is written to the Timer PWM
High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the
Timer Control register determines if the Capture occurs on a rising edge or a falling edge
of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the
timer continues counting. The INPCAP bit in TxCTL0 register is set to indicate the timer
interrupt is because of an input capture event.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting. The INPCAP bit in TxCTL0 register clears indicating
the timer interrupt is not because of an input capture event.
duration of the negative phase of the PWM signal (as defined by the difference
between the PWM registers and the Timer Reload registers).
period). The Reload value must be greater than the PWM value.
to the relevant interrupt registers.
Complement alternate functions. The Timer Output Complement function is shared
with the Timer Input function for both timers. Setting the timer mode to Dual PWM
automatically switches the function from Timer In to Timer Out Complement.
PWM Period (s)
PWM Output High Time Ratio (%)
PWM Output High Time Ratio (%)
=
------------------------------------------------------------------------------ -
System Clock Frequency (Hz)
Reload Value xPrescale
0001H
=
=
--------------------------------
Reload Value
Reload Value
------------------------------------------------------------------ -
PWM Value
is loaded into the Timer High and Low Byte
Reload Value
Z8 Encore! XP
×
–
100
PWM Value
Product Specification
×
®
100
F082A Series
Timers
77