Z8F042AHH020SC00TR Zilog, Z8F042AHH020SC00TR Datasheet - Page 167

• Manufacturer Part Number: Z8F042AHH020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHH020SC00T

Table 85. Trim Bit Data Register (TRMDR)
Table 86. Flash Option Bits at Program Memory Address 0000H
BITS
FIELD
RESET
R/W
ADDR
Flash Option Bit Address Space
BITS
FIELD
RESET
R/W
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
PS022825-0908
Trim Bit Data Register
Flash Program Memory Address 0000H
WDT_RES WDT_AO
R/W
R/W
U
7
0
7
The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim
option bits
The first two bytes of Flash program memory at addresses
for the user-programmable Flash option bits.
WDT_RES—Watchdog Timer Reset
0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a system reset. This setting is the default for unpro-
grammed (erased) Flash.
WDT_AO—Watchdog Timer Always On
0 = Watchdog Timer is automatically enabled upon application of system power. Watch-
dog Timer can not be disabled.
R/W
R/W
(Table
U
6
0
6
85).
R/W
R/W
OSC_SEL[1:0]
U
5
5
0
Program Memory 0000H
TRMDR - Trim Bit Data
R/W
R/W
U
4
0
4
FF7H
VBO_AO
R/W
R/W
U
3
3
0
Z8 Encore! XP
R/W
FRP
R/W
0000H
U
2
0
2
Product Specification
and
Reserved
0001H
R/W
R/W
U
1
1
0
®
F082A Series
Flash Option Bits
are reserved
FWP
R/W
R/W
U
0
0
0
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