Z8F042AHH020SC00TR Zilog, Z8F042AHH020SC00TR Datasheet - Page 39

• Manufacturer Part Number: Z8F042AHH020SC00TR
• Description: IC ENCORE XP MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F042AHH020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Z8F042AHH020SC00T

Stop Mode Recovery
PS022825-0908
External Reset Indicator
On-Chip Debugger Initiated Reset
and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a
pulse four cycles in duration always triggers a reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP
remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-
tus bit in the Reset Status (RSTSTAT) register is set to 1.
During System Reset or when enabled by the GPIO logic (see
on page 46), the RESET pin functions as an open-drain (active Low) reset mode indicator
in addition to the input functionality. This reset output feature allows a
Z8 Encore! XP F082A Series device to reset other components to which it is connected,
even if that reset is caused by internal sources such as POR, VBO or WDT events.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in
A Power-On Reset can be initiated using the On-Chip Debugger by setting the
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The
reset. Following the system reset the
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. See
Power Modes
ery (SMR), the CPU is held in reset for 66 IPO cycles if the crystal oscillator is disabled or
5000 cycles if it is enabled. The SMR delay (see
includes the time required to start up the IPO.
Stop Mode Recovery does not affect on-chip registers other than the Watchdog Timer
Control register (WDTCTL) and the Oscillator Control register (OSCCTL). After any
Stop Mode Recovery, the IPO is enabled and selected as the system clock. If another
system clock source is required, the Stop Mode Recovery code must reconfigure the oscil-
lator control block such that the correct system clock source is enabled and selected.
The eZ8 CPU fetches the Reset vector at Program Memory addresses
and loads that value into the Program Counter. Program execution begins at the Reset
Table 8
on page 33 for detailed STOP mode information. During Stop Mode Recov-
has elapsed.
POR
Reset, Stop Mode Recovery, and Low Voltage Detection
RST
bit in the Reset Status (RSTSTAT) register is set.
bit automatically clears during the system
Table 131
Z8 Encore! XP
on page 229) T
Port A–D Control Registers
®
Product Specification
F082A Series devices
0002H
®
F082A Series
SMR
and
RST
, also
Low-
0003H
bit in
28