MC68HC908QT2CDW

Manufacturer Part NumberMC68HC908QT2CDW
DescriptionIC MCU 1.5K FLASH W/ADC 8-SOIC
ManufacturerFreescale Semiconductor
SeriesHC08
MC68HC908QT2CDW datasheet
 

Specifications of MC68HC908QT2CDW

Core ProcessorHC08Core Size8-Bit
Speed8MHzPeripheralsLVD, POR, PWM
Number Of I /o5Program Memory Size1.5KB (1.5K x 8)
Program Memory TypeFLASHRam Size128 x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Data Converters-Connectivity-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
Page 131
132
Page 132
133
Page 133
134
Page 134
135
Page 135
136
Page 136
137
Page 137
138
Page 138
139
Page 139
140
Page 140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Page 137/184

Download datasheet (2Mb)Embed
PrevNext
15.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
Address: $FE02
Bit 7
Read:
0
Write:
Reset:
0
= Unimplemented
Figure 15-6. Break Auxiliary Register (BRKAR)
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt
15.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
Address: $FE00
Bit 7
Read:
R
Write:
Reset:
R
= Reserved
Figure 15-7. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Freescale Semiconductor
6
5
4
3
0
0
0
0
0
0
0
0
6
5
4
3
R
R
R
R
1. Writing a 0 clears SBSW.
MC68HC908QY/QT Family Data Sheet, Rev. 6
Break Module (BRK)
2
1
Bit 0
0
0
BDCOP
0
0
0
2
1
Bit 0
SBSW
R
R
(1)
Note
0
137