MC68HC908QT2CDW Freescale Semiconductor, MC68HC908QT2CDW Datasheet - Page 141

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MC68HC908QT2CDW

Manufacturer Part Number
MC68HC908QT2CDW
Description
IC MCU 1.5K FLASH W/ADC 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908QT2CDW

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
5
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
MAX232
1
16
C1+
+
1 μF
3
15
C1–
4
2
C2+
V+
+
1 μF
6
V–
5
C2–
1 μF
DB9
2
7
10
3
8
5
Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage)
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using
the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (3.2 MHz). Since this feature is enabled only
when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value
is not $FFFF) because entry into monitor mode in this case requires V
remain low during this monitor session in order to maintain communication.
Table 15-1
shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
If $FFFE and $FFFF do not contain $FF (programmed state):
The external clock is 9.8304 MHz
IRQ = V
TST
If $FFFE and $FFFF contain $FF (erased state):
The external clock is 9.8304 MHz
IRQ = V
(this can be implemented through the internal IRQ pullup)
DD
If $FFFE and $FFFF contain $FF (erased state):
IRQ = V
(internal oscillator is selected, no external clock required)
SS
Freescale Semiconductor
V
DD
+
1 μF
1 μF
+
10 kΩ
V
DD
10 kΩ
+
74HC125
5
6
74HC125
9
4
2
3
1
MC68HC908QY/QT Family Data Sheet, Rev. 6
Monitor Module (MON)
N.C.
RST (PTA3)
V
DD
N.C.
OSC1 (PTA5)
PTA1
IRQ (PTA2)
*
PTA4
PTA0
V
SS
* Value not critical
on IRQ. The IRQ pin must
TST
V
DD
0.1 μF
N.C.
N.C.
141

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