MC68HC908QT2CDW Freescale Semiconductor, MC68HC908QT2CDW Datasheet - Page 87
MC68HC908QT2CDW
Manufacturer Part Number
MC68HC908QT2CDW
Description
IC MCU 1.5K FLASH W/ADC 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QY4MDWER.pdf
(184 pages)
Specifications of MC68HC908QT2CDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
5
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
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10.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
LVI resets have been disabled
LVIOUT — LVI Output Bit
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
Freescale Semiconductor
This read-only flag becomes set when the V
when V
that prevents oscillation into and out of reset (see
DD
Address: $FE0C
voltage rises above V
Reset:
Read:
Write:
LVIOUT
Bit 7
0
= Unimplemented
.
Figure 10-2. LVI Status Register (LVISR)
V
TRIPF
MC68HC908QY/QT Family Data Sheet, Rev. 6
6
0
0
V
Table 10-1. LVIOUT Bit Indication
V
TRIPR
DD
DD
< V
V
> V
< V
DD
DD
. The difference in these threshold levels results in a hysteresis
TRIPR
TRIPF
5
0
0
< V
TRIPR
DD
DD
voltage falls below the V
4
0
0
voltage was detected below the V
Table
Previous value
10-1). Reset clears the LVIOUT bit.
R
3
0
0
LVIOUT
0
1
= Reserved
2
0
0
TRIPF
1
0
0
trip voltage and is cleared
Bit 0
TRIPF
R
0
LVI Status Register
level while
87
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