HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 459

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1.
The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.
Note:
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt
(TEI) request generation when there is no valid transmit data in TDR in MSB data transmission.
Note:
Bit 3
MPIE
0
1
Bit 2
TEIE
0
1
* When receive data including MPB = 0 is received, receive data transfer from RSR to
* TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR ,
is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR
is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Description
Multiprocessor interrupts disabled (normal reception performed)
[Clearing conditions]
Multiprocessor interrupts enabled *
Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Description
Transmit end interrupt (TEI) request disabled *
Transmit end interrupt (TEI) request enabled *
When the MPIE bit is cleared to 0
When MPB= 1 data is received
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 10, 2006 page 433 of 1042
REJ09B0275-0500
(Initial value)
(Initial value)