HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 732

• Manufacturer Part Number: HD64F2623FA20J
• Description: IC H8S MCU FLASH 256K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2623FA20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 21A Power-Down Modes [H8S/2623 Group]
21A.2.4 Module Stop Control Register (MSTPCR)
MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.
MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode.
They are not initialized in software standby mode.
MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6): These bits specify
module stop mode. See table 21A.3 for the method of selecting the on-chip peripheral functions.
MSTPCRA/MSTPCRB/
MSTPCRC Bits 7 to 0
MSTPA7 to MSTPA0,
MSTPB7 to MSTPB0,
MSTPC7 to MSTPC0
0
1
Rev. 5.00 Jan 10, 2006 page 706 of 1042
REJ09B0275-0500
MSTPCRA
Bit
Initial value :
R/W
MSTPCRB
Bit
Initial value :
R/W
MSTPCRC
Bit
Initial value :
R/W
:
:
:
:
:
:
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
R/W
R/W
R/W
7
0
7
1
7
1
Description
Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)
Module stop mode is set (initial value of MSTPA5–0, MSTPB7–0,
MSTPC7–0)
R/W
R/W
R/W
6
0
6
1
6
1
R/W
R/W
R/W
5
1
5
1
5
1
R/W
R/W
R/W
4
1
4
1
4
1
R/W
R/W
R/W
3
1
3
1
3
1
R/W
R/W
R/W
2
1
2
1
2
1
R/W
R/W
R/W
1
1
1
1
1
1
R/W
R/W
R/W
0
1
0
1
0
1