HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 150

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is
valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in write-
back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag
holds the physical address used in the external memory access. It is composed of 22 bits (address
bits 31–10) used for comparison during cache searches.
In the SH7709S, the top three of 32 physical address bits are used as shadow bits (see section 10,
Bus State Controller (BSC)), and therefore in a normal replace operation the top three bits of the
tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units
(16 bytes). The data array is not initialized by a power-on or manual reset.
LRU: With the 4-way set associative system, up to four instructions or data with the same entry
address (address bits 11–4) can be registered in the cache. When an entry is registered, the LRU
shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A
least-recently-used (LRU) algorithm is used to select the way.
The way that is to be replaced on a cache miss is determined by the 6-bit LRU. Table 5.2 shows
the correspondence between the LRU bits and the way to be replaced when the cache-lock
function is not used (when the cache-lock function is used, refer to section 5.2.2, Cache Control
Register 2 (CCR2)). If a bit pattern other than those listed in table 5.2 is set in the LRU bits by
software, the cache will not function correctly. When modifying the LRU bits by software, set one
of the patterns listed in table 5.2.
Rev. 5.00, 09/03, page 104 of 760
Entry 255
Entry 0
Entry 1
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24 (1 + 1 + 22) bits
V U Tag address
Address array (ways 0 3)
Figure 5.1 Cache Structure
255
0
1
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LW0
LW0 LW3: Longword data 0 3
128 (32
LW1
LW2
4) bits
Data array (ways 0 3)
LW3
255
0
1
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LRU
6 bits