HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 20

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.4
3.5
3.6
3.7
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
Section 5 Cache
5.1
Rev. 5.00, 09/03, page xviii of xliv
MMU Functions ................................................................................................................ 69
3.4.1
3.4.2
3.4.3
3.4.4
MMU Exceptions .............................................................................................................. 74
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Configuration of Memory-Mapped TLB........................................................................... 80
3.6.1
3.6.2
3.6.3
Usage Note ........................................................................................................................ 83
Overview ........................................................................................................................... 85
4.1.1
4.1.2
Exception Handling Function............................................................................................ 85
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
Register Descriptions......................................................................................................... 92
Exception Handling Operation .......................................................................................... 93
4.4.1
4.4.2
4.4.3
Individual Exception Operations ....................................................................................... 94
4.5.1
4.5.2
4.5.3
Cautions............................................................................................................................. 100
Overview ........................................................................................................................... 103
5.1.1
MMU Hardware Management ............................................................................. 69
MMU Software Management............................................................................... 69
MMU Instruction (LDTLB) ................................................................................. 70
Avoiding Synonym Problems............................................................................... 72
TLB Miss Exception ............................................................................................ 74
TLB Protection Violation Exception.................................................................... 75
TLB Invalid Exception......................................................................................... 76
Initial Page Write Exception ................................................................................ 77
Processing Flow in Event of MMU Exception (Same Processing Flow
for Address Error) ................................................................................................ 79
Address Array ...................................................................................................... 80
Data Array ............................................................................................................ 81
Usage Examples ................................................................................................... 83
Features ................................................................................................................ 85
Register Configuration ......................................................................................... 85
Exception Handling Flow..................................................................................... 85
Exception Vector Addresses................................................................................. 86
Acceptance of Exceptions .................................................................................... 88
Exception Codes................................................................................................... 90
Exception Request Masks .................................................................................... 91
Returning from Exception Handling .................................................................... 91
Reset..................................................................................................................... 93
Interrupts .............................................................................................................. 93
General Exceptions............................................................................................... 94
Resets ................................................................................................................... 94
General Exceptions............................................................................................... 95
Interrupts .............................................................................................................. 99
Features ................................................................................................................ 103
.................................................................................................................... 103
.......................................................................................... 85