HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 159

• Manufacturer Part Number: HD6417709SF133B
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417709SF133B

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2.05 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

The following three operations on the address array are possible.
(1) Address Array Read
Reads the tag address, LRU, U bit, and V bit from the entry that corresponds to the entry address
and w`ay that were specified in the address field. No associative operation will be performed,
regardless of the value of the associative bit (the A bit).
(2) Address Array Write (without Associative Operation)
Writes the tag address, LRU, U bit, and V bit specified in the data field to the entry that
corresponds to the entry address and way that were specified in the address field. The associative
bit (A bit) of the address field must be set to 0. An attempt to write to a cache line for which both
the U bit and V bit are set results in a write-back for that cache line. The tag address, LRU, U bit,
and V bit specified in the data field are then written. Note that, when a 0 is written to the V bit, a 0
should always be written to the U bit of the same entry, too.
(3) Address Array Write (with Associative Operation)
The associative bit (A bit) in the address field indicates whether the addresses are compared
during writing. With the A bit set to 1, all 4 ways for the entry specified in the address field will be
compared to the tag address specified in the data field for a match. The values of the U bit and V
bit specified in the data field will be written to the way that has a hit. However, the tag address and
the LRU will not be changed. If no way receives a hit, writing does not take place and the result is
no operation.
This operation is used to invalidate the address specification for a cache. Write back will take
place when the U bit of the entry that received a hit is 1. Note that, when a 0 is written to the V bit,
a 0 should always be written to the U bit of the same entry, too.
5.4.2
Data Array
The address array is mapped to H'F1000000 to H'F1FFFFFF. To access an element of the data
array, the 32-bit address field (for read/write access) and 32-bit data field (for write access) must
be specified. The address field specifies the information that selects the entry to be accessed; the
data field specifies the longword data to be written to the data array.
In the address field, specify the entry's address in bits 11-4, L in bits 3-2 to indicate the longword's
position within a line (which consists of 16 bytes), W in bits 13-12 to select the way, and H'F1 in
bits 31-24 to indicate access to the data array. The L bits (3-2) specification is in the following
form: 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3. Settings for the
W bits (13-12) are as follows: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. Since access
is not allowed crossing longword boundaries, always set 00 in bits 1-0 of the address field.
Rev. 5.00, 09/03, page 113 of 760