ISL88707IB846Z-TK

Manufacturer Part NumberISL88707IB846Z-TK
DescriptionIC SUPERVISOR MPU 4.64V 8-SOIC
ManufacturerIntersil
TypeSimple Reset/Power-On Reset
ISL88707IB846Z-TK datasheet
 


Specifications of ISL88707IB846Z-TK

Number Of Voltages Monitored1OutputOpen Drain, Push-Pull
ResetActive High/Active LowReset Timeout140 ms Minimum
Voltage - Threshold4.64VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case8-SOIC (3.9mm Width)
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesISL88707IB846Z-TKTR
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ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
V
TH1
V
DD
1V
MR
t
POR
RST
RST
FIGURE 1. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED)
Low Voltage Monitoring
These devices monitor both the voltage level of V
auxiliary voltage on PFI.
When IC is initially biased reset is asserted until the V
voltage is greater than the specific IC fixed-voltage trip point
for the t
duration of 200ms. At any subsequent time that
POR
V
does not exceed its voltage threshold, reset is once
DD
again asserted, i.e. RST is high and RST is low (see
Figure 1).
Power Failure Monitor
.
These devices also have a Power-Failure Monitor that helps
to monitor an additional critical voltage on the Power-Fail
Input (PFI) pin. For example, the PFI pin could be used to
provide an early power-fail warning, detect a low-battery
condition, presence detection or simply monitor a power
supply other than +5V. The 1.25V threshold detector can be
adjusted using an external resistor divider network to provide
custom voltage monitoring of voltages greater than 1.25V,
according to Equation 1 (see Figure 2).
R
R
+
1
2
PFI V
1.25
-------------------- -
=
TH
R
2
PFO goes low whenever PFI is less than the 1.25V (or
user-set) threshold voltage.
7
>t
MR
t
t
RPD
POR
.
and an
DD
V
IN
DD
FIGURE 2. CUSTOM V
If using a voltage divider on the PFI input to critique an
external voltage and intending to use the MR input to initiate
resets then avoid having the PFI voltage less than PFI Vth
+2.2V as unintended PFO transition may occur when MR is
transitioning high.
Adjusting t
POR
On the ISL88707 and ISL88708, users can adjust the
Power-On Reset time-out delay (t
nominal t
of 200ms. To do this, connect a capacitor
POR
between C
and ground (see Figure 3). For example,
POR
connecting a 50pF capacitor to CPOR will increase t
200ms to ~1.4s. Care should be taken in PCB layout and
capacitor placement in order to reduce stray capacitance as
(EQ. 1)
much as possible, which contributes to t
t
POR
R
1
PFI
R
2
ISL8870x
WITH RESISTOR DIVIDER ON PFI
TH
) to many times the
POR
POR
error.
POR
FN8092.5
January 12, 2009
from