X5329P-2.7A Intersil, X5329P-2.7A Datasheet - Page 8

• Manufacturer Part Number: X5329P-2.7A
• Description: IC SUPERVISOR CPU 32K EE 8-DIP
• Manufacturer: Intersil
• Type: Simple Reset/Power-On Resetr

Specifications of X5329P-2.7A

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active High
• Reset Timeout: 100 ms Minimum
• Voltage - Threshold: 2.93V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB and
RFLB instructions. The Flag bit is automatically reset
upon power-up.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an In-Circuit Programmable ROM
Figure 5. Read EEPROM Array Sequence
Status Register Bits Array Addresses Protected
BL1
0
0
1
1
SCK
SO
CS
SI
High Impedance
BL0
0
1
0
1
0
1
Instruction
8
2
3
X5328/X5329
$0C00-$0FFF
$0800-$0FFF
$0000-$0FFF
4
None
5
6
7
15 14 13
8
X5328, X5329
9
16 Bit Address
10
function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
In the locked state (
pin is LOW and the nonvolatile bit WPEN is “1”. This
mode disables nonvolatile writes to the device’s Status
Register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally.
Setting the WPEN bit in the Status Register to “0”
blocks the WP pin function, allowing writes to the Status
Register when WP is HIGH or LOW. Setting the WPEN
bit to “1” while the WP pin is LOW activates the Pro-
grammable ROM mode, thus requiring a change in the
WP pin prior to subsequent Status Register changes.
This allows manufacturing to install the device in a sys-
tem with WP pin grounded and still be able to program
the Status Register. Manufacturing can then load Con-
figuration data, manufacturing time and other parame-
ters into the EEPROM, then set the portion of memory
to be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
20 21 22 23 24 25 26 27 28 29 30
3
2
1
0
MSB
7
Programmable ROM Mode) the WP
6
5
Data Out
4
3
2
1
0
October 17, 2005
FN8132.1