ATA5760N-TGSY Atmel, ATA5760N-TGSY Datasheet - Page 12

• Manufacturer Part Number: ATA5760N-TGSY
• Description: IC RCVR UHF ASKFSK 868MHZ 20SOIC
• Manufacturer: Atmel

Specifications of ATA5760N-TGSY

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: Telemetering and Security Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

8.2
8.3
12
Bit-check Mode
Configuring the Bit Check
ATA5760/ATA5761
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge-to-edge tests before the receiver
switches to receiving mode is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verify-
ing one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The
maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N
the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N
is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the bit check takes less time if N
value. In polling mode, the bit-check time is not dependent on N
shows an example where 3 bits are tested successfully and the data signal is transferred to pin
DATA.
According to
If the edge-to-edge time t
bit-check limit T
T
Figure 8-3.
For best noise immunity it is recommended to use a low span between T
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good choice concerning that
advice. A good compromise between receiver sensitivity and susceptibility to noise is a time win-
dow of ±30% regarding the expected edge-to-edge time t
contain various edge-to-edge time periods, the bit-check limits must be programmed according
to the required span.
The bit-check limits are determined by means of the formula below.
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Lim_max
Lim_min
Lim_max
, the bit check will be terminated and the receiver switches to sleep mode.
= Lim_min
= (Lim_max – 1)
Figure
Valid Time Window for Bit Check
Lim_max
8-3, the time window for the bit check is defined by two separate time limits.
T
Dem_out
, the check will be continued. If t
XClk
ee
T
XClk
is in between the lower bit-check limit T
T
T
Lim_max
Lim_min
t
ee
1/f
Sig
ee
is smaller than T
ee
. Using pre-burst patterns that
Bit-check
.
Bit-check
Figure 8-2 on page 11
Lim_min
Lim_min
Lim_min
is set to a lower
and the upper
or t
4896D–RKE–08/08
and T
ee
Bit-check
exceeds
Lim_max
Bit-check
in
.