ATA5760N-TGSY Atmel, ATA5760N-TGSY Datasheet - Page 18

• Manufacturer Part Number: ATA5760N-TGSY
• Description: IC RCVR UHF ASKFSK 868MHZ 20SOIC
• Manufacturer: Atmel

Specifications of ATA5760N-TGSY

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: Telemetering and Security Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

9. Data Clock
9.1
18
Generation of the Data Clock
ATA5760/ATA5761
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift reg-
ister. Using this data clock, a microcontroller can easily synchronize the data stream. This clock
can only be used for Manchester and Bi-phase coded signals.
After a successful bit check, the receiver switches from polling mode to receiving mode and the
data stream is available at pin DATA. In receiving mode, the data clock control logic (Man-
chester/Bi-phase demodulator) is active and examines the incoming data stream. This is done,
like in the bit check, by subsequent time frame checks where the distance between two edges is
continuously compared to a programmable time window. As illustrated in
only two distances between two edges in Manchester and Bi-phase coded signals are valid (T
and 2T).
The limits for T are the same as used for the bit check. They can be programmed in the
LIMIT-register (Lim_min and Lim_max, see
26).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Upper limit of 2T:
(If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it will be round up)
The data clock is available, after the data clock control logic has detected the distance 2T (Start
bit) and is issued with the delay t
If the data clock control logic detects a timing or logical error (Manchester code violation), like
illustrated in
clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was
successful and the start bit has been detected, the data clock control logic starts again with the
generation of the data clock (see
It is recommended to use the function of the data clock only in conjunction with the bit check 3, 6
or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the pin POLLING/_ON,
the data clock is available if the data clock control logic has detected the distance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 9-2 on page 19
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
Delay
Figure 9-4 on page
and
after the edge on pin DATA (see
Figure 9-3 on page
Table 11-10 on page 26
20).
19, it stops the output of the data
and
Figure 9-1 on page
Figure 9-1 on page
Table 11-11 on page
4896D–RKE–08/08
19).
19,