ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 263
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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2467V–AVR–02/11
Table 104. Boundary-scan Signals for the ADC (Continued)
Note:
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
Cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
Signal
Name
MUXEN_7
MUXEN_6
MUXEN_5
MUXEN_4
MUXEN_3
MUXEN_2
MUXEN_1
MUXEN_0
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
Incorrect setting of the switches in
part. There are several input choices to the S&H circuitry on the negative input of the output com-
parator in
reference source, or Ground.
Direction
as Seen
from the
ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Figure
131. Make sure only one path is selected from either one ADC pin, Bandgap
Description
Input Mux bit 7
Input Mux bit 6
Input Mux bit 5
Input Mux bit 4
Input Mux bit 3
Input Mux bit 2
Input Mux bit 1
Input Mux bit 0
Input Mux for negative
input for differential signal,
bit 2
Input Mux for negative
input for differential signal,
bit 1
Input Mux for negative
input for differential signal,
bit 0
Enable pass-gate of gain
stages.
Precharge output latch of
comparator. (Active low)
Switch-cap TEST enable.
Output from x10 gain
stage send out to Port Pin
having ADC_4
Output of gain stages will
settle faster if this signal is
high first two ACLK
periods after AMPEN goes
high.
Selects Vcc as the ACC
reference voltage.
Figure 131
will make signal contention and may damage the
Recommended
Input
when not
in Use
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
ATmega128
Table 104
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
should
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